Heterogeneous IC Integration

Without surface mounts
With surface mounts

As system performance requirements and complexity continue to grow with an emphasis on SWAP, it is inevitable that heterogeneous IC integration will become the industry standard. The conventional monolithic system on a chip is just not economically feasible to integrate all of the functionality onto one universal technology node. FPGA alone cannot include mixed signal, analog and RF functions as these technologies have vastly diverging requirements. Attempts have been made to combine programmable logic with analog and memory. There is either too little memory, logic or analog performance. These result in a very restricted product offering and as such limit the range of applications that will fit within these constraints. A much more versatile product results from the integration of components that have been constructed on an optimum technology node for each function. The integration of sensors (MEMs), RF, A/D, CPU, ASIC, DRAM, Flash and III-V materials into a single module produces a SIP with far higher functionality, better SWAP, and performance unachievable with any other approach.


Lowest SWaP (Size, weight, and Power)

SWAP reduction steps

A significant trend in electronics today is the reduction of size weight and power (SWAP). Particularly for portable applications where size, or volume, and weight become critical to the ability to carry electronic equipment in the field. For portable applications, power reduction is equally important in as much as the power supply size and weight becomes a significant factor. Even for stationary applications size and power are critical as it may affect the size of the server farm or facility size, and the power service requirements. The benefits of SWAP are obvious, but how to achieve a very low SWAP for cases where a full ASIC design may not be available or applicable. The figure to the right depicts a series of intuitive actions that reduce SWAP. Eliminate the semiconductor package size and volume by using bare die. Bare die may be obtained through a die extraction methodology, or purchased directly from the OCM. The bare die are thinned to a uniform thickness. The die for the SIP MCM are placed in close proximity, compared to normal packaging methods. This immediately minimizes size and weight in two out of the three axes. The third axis is accomplished through stacking of modules.


Heterogeneous Multichip Modules

Heterogeneous Multichip Modules are a chips-first, fan out, wafer level package.

  • Heterogeneous IC integration
  • Embedded active and passive die in the smallest volume form factor
  • Ultra-high density interconnect
  • Front-to-back interconnect TSVs (Through Substrate Vias)
  • More robust system design than commercial off-the-shelf

Single Sub-Module Overview


Interconnect Fabric

Seven interconnect layers are possible on both the frontside and the backside, allowing for design possibilities such as controlled impedance transmission lines, power/ground bus, and signal line shielding for crosstalk isolation.

Multichip module, bare die, pre-interconnect

Multichip module, post-interconnect


3D Stacking with Heterogeneous MCMs

Individual Multichip Modules can be stacked for higher performance in the same footprint.

Three stacked modules are thinner than a credit card.

Proven Quality

With the help of our partners, world-class quality is intrinsic in our products. Since 2008, we have produced over 3,000 Heterogeneous Multichip Modules. These MCMs are deployed in complex, high-reliability systems with no returns.

The Heterogeneous MCM technology was developed for the military market (low volume, high mix) on 100mm wafers. We are transferring this technology to larger wafers to support higher volume, lower cost commercial markets.